1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device and, more particularly, to an electrically erasable semiconductor memory device. More specifically, it relates to a batch erasing type flash EEPROM, that is, an electrically erasable read only memory.
2. Description of the Background Art
FIG. 1 shows an example of the overall structure of a conventional non-volatile semiconductor memory device. Referring to this figure, the non-volatile semiconductor memory device includes a memory cell array 1 comprised of a plurality of memory cells for non-volatile data storage. As will become apparent hereinafter, the memory cell array 1 is comprised of a plurality of word lines arranged in a row direction, a plurality of bit lines in a column direction and memory cells each provided at each intersection point between a word line and a bit line.
An X address buffer 2 and an X decoder 3 are provided for selecting a row of the memory cell array 1. The X address buffer 2 is supplied with an X address from an exterior of the device to produce an internal row address. The X decoder 3 decodes the internal row address from the X address buffer 2 to select an associated row in the memory cell array 1 to transmit an activating signal on the selected word line.
A Y address buffer 4 and a Y decoder 5 are provided for selecting columns of the memory cell array 1. The Y address buffer 4 is supplied with a Y address from the exterior to produce an internal column address. The Y decoder 5 decodes the internal column address from the Y address buffer 4 to produce a signal for selecting associated columns.
A column select gate 6, a write driver 7, a sense amplifier 8, an ECC (error checking and correction) circuit 9, an input buffer 10 and an output buffer 11 are provided to effect data exchange between the memory cell array 1 and a device or devices outside the memory device. A column select gate 6 is responsive to the column select signal from the Y decoder 5 to connect associated columns of the memory cell array 1 to the write driver 7 and the sense amplifier 8 via I/O lines, that is inner data transmission lines. The write driver 7 transmits the data supplied thereto in data writing to the selected memory cells via column select gate 6. The sense amplifier 8 is activated in data reading to amplify and output data supplied thereto via column select gate 6. The ECC circuit 9 takes charge of detection and correction of data errors. The ECC circuit 9 produces parity bits for data error detection/correction in accordance with, for example, the Hamming Coding Method, for write data Din supplied thereto via input buffer 10 to transmit the produced parity bits to the write driver 7 in parallel with the write data Din. In data reading out, the ECC circuit 9 similarly produces check bits for the data supplied thereto via sense amplifier 8 to effect comparison between the read-out parity bits and the produced check bits to detect and correct data errors based on the results of comparison to supply the corrected data to the output buffer 11. The data supplied to the input buffer 10 and the output buffer 11 are subjected to waveform shaping before being outputted from these buffers 10, 11.
An electrically erasable ROM (EEROM), having the function of error detection/correction as shown in FIG. 1 is shown by S. Mehrotra et al. in IEEE, International Solid-State Circuit Conference 1984, Digest of Technical Papers, pages 142 to 143.
For defining various operational timings in the above described semiconductor memory device, there is provided a control signal generator 12 which is responsive to write enable signals WE, output enable signal OE and chip enable signals CE or chip select signal CS supplied thereto from an exterior of the device to produce various timing control signals. In FIG. 1, a semiconductor chip is indicated by a broken-line block 100.
FIG. 2 shows the structure of a major part of the semiconductor memory device shown in FIG. 1. Although one byte usually means 8 bits, it is assumed that, in the construction illustrated in FIG. 2, each byte is constituted by 2 bit memory cells for purpose of clarity of the disclosure. Each memory cell is constituted by a selection transistor Qi, i being 1 to 8, and a memory transistor Mi, i being 1 to 8. The selection transistor Qi has its drain connected to a bit line BLi, its gate to the word line WL, and its source to the drain of the associated memory transistor Mi. The memory transistor Mi is constituted by a floating gate type insulated gate field effect transistor. The memory transistor Mi has its control gate connected to a control gate line CGL, via an insulated gate type field effect transistor or MOS transistor Q9, while having its source connected to a ground potential via MOS transistor Q10. The transistor Q10 is rendered conductive in erasure and reading-out modes to ground the source line while it is rendered non-conductive to bring the source line into an electrically floating state in a programming mode.
The MOS transistor Q9 has its gate connected to the word line WL. A source line select signal SL is applied to the gate of the MOS transistor Q10.
The bit lines BL1 to BL8 are connected to data input/output lines I/O1 and I/O2 via MOS transistors Q11 to Q18 functioning as column select gates. Thus the bit line BL1 is connected to the input/output line I/O1 via MOS transistor Q11, while the bit line BL2 is connected to the input/output line I/O2 via MOS transistor Q12. The bit line BL3 is connected to the input/output line I/O1 via MOS transistor Q13, while the bit line BL4 is connected to the input/output line I/O2 via MOS transistor Q14. The bit lines BL5 and BL6 are connected to the input/output lines I/O1 and I/O2 via MOS transistors Q15 and Q16, respectively. The bit line BL7 and BL8 are connected to the input/output lines I/O1 and I/O2 via MOS transistors Q17 and Q18, respectively.
A Y gate signal, that is, a column select signal Y1 is applied from the Y decoder 5 to the gates of the MOS transistors Q11 and Q12. A Y gate signal Y2 is applied from the Y decoder 5 to the gates of the MOS transistors Q13 and Q14. A Y gate signal Y3 is applied from the Y decoder 5 to the gates of the MOS transistors Q15 and Q16. A Y gate signal Y4 is applied to the gates of the MOS transistors Q17 and Q18 from the Y decoder 5. The above described arrangement allows performing data writing/reading into and out of 1-byte memory cells at a time.
The row select signal from the X decoder 3 is applied via MOS transistor Q19 to the word line WL for row selection. A Vpp switch 20, adapted for further raising the potential of a word line WL which is in the selected state during data writing, is connected to the word line WL. A predetermined potential, such as the source (power supply) potential Vcc, is applied to the gate of the MOS transistor Q19, which thus has the function of preventing the high voltage generated during the operation of the Vpp switch 20 from affecting an output circuit portion of the X decoder 3.
The X decoder 3 has, for each word line, a NAND gate 31 and an inverter 32 adapted for receiving an output of the NAND gate 31. The row select signal is generated by the inverter 32.
The cross-section of a memory cell is shown diagrammatically in FIG. 3. Referring to this figure, the memory transistor includes an N.sup.+ impurity region 201 acting as a source, an N.sup.+ impurity region 202 acting as a drain and, a floating gate 203 and a control gate 204. An interlayer insulating film 208 is formed between the floating gate 203 and the control gate 204. A gate insulating film 207 is formed between the floating gate 203 and a semiconductor substrate 200. A tunnel insulating film 209 of a reduced film thickness is formed between the floating gate 203 and the drain region 202. Exchange of electrons between the floating gate 203 and the drain region 202 occurs by way of this tunnel insulating film 209.
A selection transistor includes an N.sup.+ impurity region 202 acting as a source, an N.sup.+ impurity region 205 acting as a drain and a gate electrode 206. A gate insulating film 210 is formed between the gate electrode 206 and the semiconductor substrate 200. The N.sup.+ impurity region 205 is connected to the bit line BL.
In the above described memory cell structure, data storage is performed depending on the amount of the electrical charges stored in the floating gate 203. That is, when a high electrical voltage Vpp is applied to the control gate 204, and the N.sup.+ impurity region is at the ground potential, the electrons are injected, by the resultant high electrical field, via the tunnel insulating film 209 into the floating gate 203. This causes the threshold voltage of the memory transistor to be shifted in the positive direction. Conversely, when the N.sup.+ impurity region 202 is at the high voltage Vpp and the control gate 204 is at the ground potential level, the electrical charges are extracted from the floating gate 203 into the N.sup.+ impurity region 202. This causes the threshold voltage of the memory transistor to be shifted in the negative direction.
During data read-out, a predetermined read-out voltage is applied to the control gate 204. During selection, a logical high or "H" level potential is applied to the gate of the selection transistor 206. The memory transistor is turned on or off depending on the amount of the electrical charges stored in the floating gate 203. With the selection transistor in the turned-on state, a current flow is or is not caused through the bit line BL when the memory transistor is in the turn-on or in the turn-off state, respectively. The current flow on the bit line BL is sensed by the sense amplifier so as to be converted into a voltage signal to permit read-out of the "1" or "0" data.
The Vpp switch 20 shown in FIG. 2 has a construction as shown in FIG. 4. Referring to FIG. 4, the Vpp switch 20 includes MOS transistors Q101, Q102 and a capacitor C1. The MOS transistor Q101 has its drain connected to the high voltage Vpp and its gate connected to the source of the transistor Q102 and to the word line WL, while having its source connected to the drain and the gate of the MOS transistor Q102 and to one electrode of the capacitor C1. The other electrode of the capacitor C1 is fed with control clock signals CLK. This Vpp switch 20 operates such that, when the potential on the word line WL is at the "H" level, and hence the MOS transistor Q101 is in the turn-on state, the potential corresponding to the potential on the word line WL is applied to one electrode of the capacitor C1 and to the drain and the gate of the transistor Q102. When the control clock signals CLK are supplied to the Vpp switch 20 in the form of a repetition of pulses, the potential at the one electrode of the capacitor C1 is gradually raised by its bootstrap function for each clock pulse. The thus raised voltage is transmitted to the word line WL via a MOS transistor Q102. The increased potential is applied to the gate of the MOS transistor Q101 to raise the potential at the node ND through the transistor Q101 by the supply of a voltage from the Vpp generator. By the repetition of the above operation, the potential on the word line WL ultimately reaches the high voltage Vpp level.
With the potential on the word line at the "L" level, the transistor Q101 is in the turn-off state and no voltage is supplied to the one electrode of the capacitor C1, so that transistor Q102 is not turned on, and the potential on the word line WL remains at the logical low or "L" level.
The operation of the non-volatile semiconductor memory device shown in FIG. 2 will be explained with referring to FIGS. 3 and 4. Although the semiconductor memory device of FIG. 2 may be operated in both flash erasure and page erasure modes, the following description will be made of the page erasure mode type operation.
The operation in the semiconductor memory device includes data writing and data reading. The page writing operation is first explained. The data writing operation includes external writing operation and internal writing operation. In the external writing operation, memory cells are selected responsive to the X and Y addresses supplied externally. More specifically, a corresponding word line WL is selected by the X decoder 3. The potential on the selected word line WL is raised at this time to the logical high level. On the other hand, one of the Y gate signals Yi, wherein i indicates numerals 1 to 4, is raised to the logical high level, so that the bit lines are connected to the input-output lines. Write data are transmitted to this selected bit lines via write driver 7 (FIG. 1).
It is now assumed that the Y gate signal Y1 is at the logical high level and the bit lines BL1, BL2 are connected to the input/output lines I/O1 and I/O2. At this time, the write data are transmitted to the bit lines BL1 and BL2. The data transmitted on these bit lines BL1 and BL2 are latched by latch means or column latches, not shown. This operation is repeated a predetermined number of times on one word line WL to effect writing of data for one page, or of a predetermined number of data. Such data writing is performed by activating the control signals WE and CE to the low level. After termination of writing of the predetermined number of data, external accessing is inhibited by the operation of a built-in timer or the control signal WE. The internal writing operation is now initiated.
This internal writing includes an erasure operation and a programming operation. During erasure operation, the data in the memory cells connected to the selected word line are all erased. During this mode, the potential on the control gate line CGL is raised to Vpp. Such voltage increase on the control gate line CGL is performed by, for example, control circuit means, not shown. On the other hand, the bit lines BL1 to BL8 are all set to the logical low level. Since the Y gate signals Y1 to Y4 are all at the logical low level, setting the bit lines BL1 to BL8 to the logical low level is performed by turning on the internal transistor switches, not shown, provided for each of the bit lines BL1 to BL8. On the other hand, the source line select signal SL is set to the logical high level. This renders the transistor Q10 conductive so that the source lines of the memory transistors M1 to M8 are all connected to receive the ground potential. In this state, the Vpp switch 20 is activated and the potential on the word line WL in the selected state is raised to a Vpp level higher than the logical high level. As a result, the high voltage Vpp on the control gate lines CGL is transmitted via transistor Q9 to control gates of the memory transistors M1 to M8. On the other hand, the drain electrodes of the memory transistors M1 to M8 are connected to the bit lines BL1 to BL8 via select transistors Q1 to Q8 and are in the logical low level. This causes electrons to be injected into the floating gates (203 in FIG. 3) of the memory transistors M1 to M8, to lead to termination of the erasure operation, that is, page erasure, of the memory transistors M1 to M8. This erased state corresponds to the state that the data " 1" is written.
The programming operation is then performed. During this programming operation, data writing is performed only into the memory cells into which data "0" are to be written. For this programming mode, the potential on the control gate line CGL is set to the logical low level. On the other hand, the potential on the bit line to which a memory transistor undergoing the programming is connected is raised to the high voltage Vpp, while the potential on the other bit lines is set to the logical low level. Potential transmission to these bit lines is performed by activating the Vpp switch in accordance with the data latched by the column latches associated with the bit lines.
For example, when only the memory transistor M1 is programmed, the potential on the bit line BL1 is raised to the high voltage Vpp level by the Vpp switch and the column latch, not shown, the remaining bit lines BL2 to BL8 being set to the logical low level potential. During the programming operation, the source line select signal SL is at the logical low level, the MOS transistor Q10 is turned off, and the sources of the memory transistors M1 to M8 are in the electrically floating state. Under this condition, the word line WL is raised to the high voltage Vpp by the operation of the Vpp switch 20. The control gate line CGL is now at the ground potential, the bit line BL1 is at the high voltage Vpp and the word line WL is at the high voltage Vpp. Thus the high potential Vpp is transmitted to the drain of the memory transistor M1, while the control gate of the memory transistor M1 is at the ground potential GND. This causes electrons to be extracted from the floating gate of the memory transistor M1 to complete the programming. This state corresponds to the state that the data "0" is written.
In the flash erasure type semiconductor memory device, the word lines are all activated to effect data erasure of all the memory cells before proceeding to data writing, after which data writing or programming is performed in the same manner as described hereinabove.
The operation of reading out data is now explained. During data reading, the memory cells are selected similarly by the X and Y addresses. It is now assumed that the 1-byte data provided by the memory transistors M1 and M2 is to be read out. At this time, the Y gate signal Y1 from the Y decoder 5 is at the logical high level, while the potential on the word line WL is also at the logical high level by the output from the X decoder 3. The read-out potential, such as 0 V or a predetermined positive voltage, is supplied to the control gate line CGL. This read-out potential is set to a voltage intermediate between the threshold voltage of the memory transistor in the erased state and the threshold voltage of the memory transistor in the programmed state. It is now assumed that the memory transistor M1 is in the erased state, that is, stores data "1", with electrons injected therein, while the memory transistor M2 is in the programmed state and stores data "0". At this time, the memory transistor M1 is off, while the memory transistor M2 is on. During the read-out operation, the source line select signal SL is at the logical high level, while the transistor Q10 is in the turn-on state. Hence, the current flows from the bit line BL2 to the ground potential by way of transistors Q2, M2 and Q10, such current not flowing through the bit line BL1. This change in the current flow through the bit lines BL1 and BL2 is sensed by the sense amplifiers (8 in FIG. 1) connected to the input/output lines I/O1 and I/O2 so as to be converted into corresponding voltage signals that are to be transmitted to the ECC circuit.
Therefore, in the construction shown in FIG. 2, data are written and read out on the byte by byte basis.
In the above described conventional non-volatile semiconductor device, the high voltage Vpp is supplied to the gates of the select transistors Q1 to Q9 during data writing (flash erasure, page erasure and programming mode). The purpose of applying this high voltage Vpp is to cause a tunneling current to be produced in the memory transistors M1 to M8. For such tunneling current to be produced in the memory cell transistors M1 to M8, it is necessary to apply a high electric field of ten mega volts/cm between the floating gate 203 and the drain region 202 (FIG. 3). The film thickness of the gate insulating film is usually selected to be of the order of ten nanometers. For application of such high electrical field, it is necessary to employ the high voltage Vpp of the order 16 to 20 V.
On the other hand, the purpose of providing the gate insulating film of the selection transistor is simply to form a channel layer or an inversion layer for turning on and off of the transistor, and the film thickness of the gate insulating film is selected to be several tens of nanometers. However, when such high voltage Vpp is applied to the gate insulating film, the repetitive operation of writing results in destruction of the gate insulating film (the word line destruction) to cause current leakage between the drain region and the gate electrode in the selection transistor to give rise to an inconvenience that the potential on the word line is not raised to the high voltage Vpp, or the logical high level.
In such case, a selected memory cell is in the non-selected state and hence accurate data writing and/or reading cannot be realized, thus lowering the reliability of the non-volatile semiconductor memory device.
For improving the reliability of the non-volatile semiconductor memory device, it is effective to apply error detection and correction on the read-out data using error correction code. However, for performing error detection/correction using the ECC circuit, it is necessary to store not only information bits but also parity bits, while it is necessary during data read-out to produce check bits from the read-out data to compare the parity bits and the check bits with each other.
If the Hamming Codes are employed, error checking/correction such as t-plex error correction/detection may be performed. However, for a higher integration of the non-volatile semiconductor memory device, the area occupied by the ECC circuit and the parity bit storage region should be made as small as possible. For this reason, 1-bit error correction code (SEC) or a 1-bit error correction 2-bit error detection code (SEC-DED) is preferred for the error correction code.
On the other hand, in the above described conventional non-volatile semiconductor memory device, the 1-byte data to be read out simultaneously are read out from the memory transistors arranged on the same word line. Hence, on occurrence of the above described word line destruction, the read-out 1-byte data are all in error. Even if the above described error correction codes are employed, it becomes impossible to effect detection and correction for all of the 1-byte data. Thus, in case of the word line destruction, it becomes impossible to effect accurate data reading. Therefore, in the conventional construction, it is not possible to cope with the word line destruction.
A divided word line structure in which a word line comprises a major word line and a plurality of auxiliary-word lines each connected to the major word line through a logic gate is disclosed in, for example, reissued U.S. Pat. Nos. 32,993 and No. 33,280.
This structure is adopted to reduce the access time of a memory, not to repair a destroyed word line in an EEPROM.